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Introduction to Verilog
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This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.
In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.
Level
Fundamental to Intermediate
Duration
3 Days
Who Should Attend
Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs
Software Tools
ISE™ 9.1i
Xilinx ISIM Simulator
Synplicity Synplify Pro
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
Write RTL Verilog code for synthesis
Write Verilog test fixtures for simulation
Create a Finite State Machine (FSM) by using Verilog
Target and optimize Xilinx FPGAs by using Verilog
Use enhanced Verilog file I/O capability
Run a timing simulation by using Xilinx Simprim libraries
Create and manage designs by using the ISE software design environment
Course Outline
Day 1
Hardware Modeling Overview
Verilog Language Concepts
Memories, Modules, and Ports
Lab 1: Building Hierarchy
Introduction to Testbenches
Lab 2: Verilog Simulation and RTL Verification
Operators and Expressions
Day 2
Data Flow-Level Modeling
Lab 3: Memory
Verilog Procedural Statements
Controlled Operation Statements
Lab 4: n-bit Binary Counter and RTL Verification
Advanced Language Concepts
Lab 5: Comparator
Day 3
Tasks and Functions
Lab 6: Arithmetic Logic Unit
Finite State Machines
Lab 7: Finite State Machines
Targeting Xilinx FPGAs
Lab 8: Calculator
Advanced Verilog Testbenches
Lab 9: Using Verilog File I/O
Labs
The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.
Prerequisites
Basic digital design knowledge
No Scheduled Sessions
Contact Bottom Line Technologies for more information
Education Investment Options
| Course & Basic Follow-on Coaching |
$1,949 |
REGISTER |
| Course & Comprehensive Follow-on Coaching |
$2,399 |
REGISTER |
| Course Only |
$1,799 |
REGISTER |
| Basic Coaching ala Carte |
Not currently offered |
REGISTER |
| S3 Board & 1 hour support |
$399 |
REGISTER |
| V4 Board & 1 hour support |
$599 |
REGISTER |
| V5 Board & 1 hour support |
$1,399 |
REGISTER |
Basic follow-on coaching includes 2 hours (max 4 calls)
Comprehensive follow-on coaching includes 8 hours (max 12 calls)
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