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Introduction to AccelDSP
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Learn how to synthesize an algorithm written in the language of MATLAB® software into a design that is optimized for a Xilinx FPGA. Find out how to make coding changes in MATLAB® software that improve area and performance. Use the floating- to fixed-point and design exploration features of the AccelDSP™ synthesis tool to achieve maximum results. Merge a synthesized MATLAB® software block into a larger HDL design or System Generator design.
Level
Fundamental
Duration
2 Days
Who Should Attend
Engineers seeking to develop the necessary skills for designing DSP systems using Xilinx AccelDSP synthesis tool running with MATLAB® software
Software Tools
Xilinx ISE™ 9.2.02i
Xilinx AccelDSP Synthesis Tool 9.2
MATLAB R2007a
Xilinx System Generator 9.2
Mentor Graphics ModelSim PE 6.2f
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
Transform a non-synthesizable MATLAB® software algorithm into a design that can be synthesized by the AccelDSP™ synthesis tool
Identify the concepts of quantization as well as specify, monitor, and control bit growth in a MATLAB® design
Modify the MATLAB® software design for a direct form FIR filter into a synthesizable polyphase decimation filter
Apply coding style changes and AccelDSP™ directives to optimize a design for performance and efficiency
Write MATLAB® coding changes to add hardware control features to a design
Merge a synthesized MATLAB® block into a larger HDL design
Export and merge a synthesized MATLAB® block into a larger System Generator design
Course Outline
Day 1
Introduction to AccelDSP™ Synthesis
Synthesizable MATLAB®
Quantization
Multirate Design
Using AccelWare
Day 2
Design Exploration
Adding Hardware Control
Coding for Hardware Performance
Synthesizing Complex Numbers
Interfacing to System Hardware
System Generator Integration
Labs
Lab 1: Getting Started with AccelDSP – Learn the basic design flow through the AccelDSP synthesis tool.
Lab 2: Synthesizable MATLAB – Modify an unsynthesizable MATLAB software design into a design that can be synthesized by the AccelDSP synthesis tool.
Lab 3: Quantization – Specify, monitor, and control bit growth in the synthesized design.
Lab 4: Multirate Design – Set up the design to model the effects of decimation by 2. Create a synthesizable polyphase decimation filter in MATLAB software and implement the filter in a XilinxFPGA.
Lab 5: Using AccelWare – Replace a polyphase decimation filter with an equivalent FIRdecim AccelWare™ DSP IP tool kit block.
Lab 6: Design Exploration – Apply the design exploration features of the AccelDSP synthesis tool to optimize a design for area and performance.
Lab 7: Adding Hardware Control – Modify the source of a FIR filter to add a serial coefficients load feature.
Lab 8: Coding for Hardware Performance – Learn MATLAB software coding techniques to take advantage of even-symmetric coefficients and drive performance over 300 MHz.
Lab 9: Synthesizing Complex Numbers – Explore the methods available for synthesizing designs that use complex numbers.
Lab 10: Interfacing to System Hardware – Connect the interface signals generated in the AccelDSP synthesis tool to a larger HDL design.
Lab 11: System Generator Integration – Convert a MATLAB based design into a System Generator block and merge the block into a larger System Generator design.
Prerequisites
- Fundamentals of MATLAB®
- Basics of digital signal processing theory
No Scheduled Sessions
Contact Bottom Line Technologies for more information
Education Investment Options
| Course & Basic Follow-on Coaching |
$1,599 |
REGISTER |
| Course & Comprehensive Follow-on Coaching |
$2,199 |
REGISTER |
| Course Only |
$1,399 |
REGISTER |
| Basic Coaching ala Carte |
Not currently offered |
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| S3 Board & 1 hour support |
$399 |
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| V4 Board & 1 hour support |
$599 |
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| V5 Board & 1 hour support |
$1,399 |
REGISTER |
Basic follow-on coaching includes 2 hours (max 4 calls)
Comprehensive follow-on coaching includes 8 hours (max 12 calls)
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