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Fundamentals of FPGA Design
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Use the ISE™ software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.
This course covers ISE 9.1i features, such as the Architecture Wizard and the Floorplan Editor. Other topics include design planning, implementation options, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.
Note that one of the prerequisites of Fundamentals of FPGA Design is the completion of the basic FPGA architecture modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.
Level
Fundamental
Duration
1 Day
Who Should Attend
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
Software Tools
Xilinx ISE 9.1i
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
Use Xilinx Project Navigator to implement an FPGA design
Assign pin locations with the Floorplan Editor tool
Create DCM instantiations with the Architecture Wizard
Read reports to determine whether design goals were met
Use the Constraints Editor to enter basic global timing constraints
Locate and modify implementation options
Course Outline
Course Agenda
Xilinx Tool Flow
Lab 1: Xilinx Tool Flow Lab
Reading Reports
Lab 2: Architecture Wizard and Floorplan Editor Lab
Lab 3: Pre-Assigning I/O Pins Lab
Global Timing Constraints
Lab 4: Global Timing Constraints Lab
Implementation Options
Lab 5: Implementation Options Lab
Synchronous Design Techniques
Course Summary
Labs
Lab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the Architecture Wizard and the Floorplan Editor in the design process. Implement a design by using default software options. The design will be simulated.
Lab 2: Architecture Wizard and Floorplan Editor – Use the Architecture Wizard to customize a DCM and incorporate the DCM into the design. Use the Floorplan Editor to assign pin locations and implement the design.
Lab 3: Pre-Assigning I/O Pins – This lab introduces the basics of making good I/O pin assignments with the Floorplan Editor. Use the SSO Analyzer to avoid ground bounce and the Design Rule Checker to follow the I/O Banking Rules.
Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.
Lab 5: Implementation Options – Adjust process properties and I/O configuration options to improve the design performance.
Prerequisites
* Opens new window on Xilinx Website
Scheduled Sessions
Education Investment Options
| Course & Basic Follow-on Coaching |
$749 |
REGISTER |
| Course & Comprehensive Follow-on Coaching |
$1,199 |
REGISTER |
| Course Only |
$599 |
REGISTER |
| Basic Coaching ala Carte |
Not currently offered |
REGISTER |
| S3 Board & 1 hour support |
$399 |
REGISTER |
| V4 Board & 1 hour support |
$599 |
REGISTER |
| V5 Board & 1 hour support |
$1,399 |
REGISTER |
Basic follow-on coaching includes 1 hour (max 2 calls)
Comprehensive follow-on coaching includes 4 hours (max 6 calls)
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