|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
Multi-Gigabit Serial I/O Design
|
Learn how to employ RocketIO™ GTP serial transceivers in your Virtex™-5 LXT FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as CRC, 8B/10B encoding, channel bonding, clock correction, and comma detection. Additional highlighted topics include use of the Architecture Wizard and synthesis and implementation considerations. This course balances lecture modules and practical hands-on labs.
Level
Intermediate
Duration
2 Days
Who Should Attend
FPGA designers and logic designers
Software Tools
Xilinx ISE™ 9.1i
Mentor Graphics ModelSim PE 6.2
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
Describe and utilize the ports and attributes of the RocketIO™ multi-gigabit transceiver (GTP) in the Virtex™-5 LXT FPGA
Effectively use the following features of the GTP
Comma detection, CRC, clock correction, and channel bonding
8B/10B encoding/decoding, programmable termination, and preemphasis
Use the GTP Wizard to instantiate GTP primitives in a design
Access appropriate reference material for board design issues
Power supply, oscillators, and trace design
Course Outline
Day 1
Introduction
Clocking and Resets
8B/10B Encoder and Decoder Details
Lab 1: 8B/10B Disparity and Bypass
Commas and Data Alignment Details
Lab 2: Commas and Data Alignment
Cyclical Redundancy Check Details
Lab 3: Cyclical Redundancy Check
Day 2
Clock Correction Details
Lab 4: Clock Correction
Channel Bonding Details
Lab 5: Channel Bonding
GTP Wizard Overview
Implementing a RocketIO Transceiver Design
Lab 6: Synthesis and Implementation
Physical Media Attachment Overview
Labs
Lab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.
Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.
Lab 3: CRC – Configure a CRC block using the CRC Wizard.
Lab 4: Clock Correction – Utilize the clock correction logic to compensate for frequency differences on the TX and RX side of a link.
Lab 5: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.
Lab 6: Synthesis and Implementation – Use the GTP Wizard to configure RocketIO transceiver primitives. Instantiate the resulting component in a design, synthesize the design, and implement the design.
Prerequisites
- Verilog or VHDL experience or the Introduction to Verilog or Introduction to VHDL
- Synthesis and simulation experience
- FPGA design experience or the Fundamentals of FPGA Design course
- Knowledge of high-speed serial I/O protocols and standards (SONET, Gigabit Ethernet, InfiniBand) is a plus
No Scheduled Sessions
Contact Bottom Line Technologies for more information
Education Investment Options
| Course & Basic Follow-on Coaching |
$1,599 |
REGISTER |
| Course & Comprehensive Follow-on Coaching |
$2,199 |
REGISTER |
| Course Only |
$1,399 |
REGISTER |
| Basic Coaching ala Carte |
Not currently offered |
REGISTER |
| S3 Board & 1 hour support |
$399 |
REGISTER |
| V4 Board & 1 hour support |
$599 |
REGISTER |
| V5 Board & 1 hour support |
$1,399 |
REGISTER |
Basic follow-on coaching includes 2 hours (max 4 calls)
Comprehensive follow-on coaching includes 8 hours (max 12 calls)
|
|
|
|
