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Designing for Performance
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Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design in a smaller FPGA or lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.
Level
Intermediate
Duration
2 Days
Who Should Attend
FPGA designers with intermediate knowledge of HDL and some experience with the Xilinx ISE™ software tools.
Software Tools
Xilinx ISE 9.1i
Synplicity Synplify Pro
Mentor Graphics Precision RTL
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
Describe a flow for obtaining timing closure
Describe architectural features of the Virtex™-4 FPGA
Describe the features of the Digital Clock Manager (DCM) and Phase-Matched Clock Divider (PMCD) and how they can be used to improve performance
Increase performance by duplicating registers and pipelining
Write HDL code by using a style that is optimal for targeting Xilinx devices
Describe different synthesis options and how they can improve performance
Create and integrate cores into your design flow by using the CORE Generator™ software system
Run behavioral simulation on an FPGA design that contains cores
Pinpoint design bottlenecks by using the Timing Analyzer reports
Apply advanced timing constraints to meet your performance goals
Use advanced implementation options to increase design performance
Course Outline
Day 1
Review of Fundamentals of FPGA Design
Designing with Virtex-4 FPGA Resources
CORE Generator Software System
Lab 1: CORE Generator Software System
Designing Clock Resources
Lab 2: Designing Clock Resources
FPGA Design Techniques
Synthesis Techniques
Lab 3: Synthesis Techniques
Day 2
Achieving Timing Closure
Lab 4: Review of Global Timing Constraints
Timing Groups and OFFSET Constraints
Path-Specific Timing Constraints
Lab 5: Achieving Timing Closure
Advanced Implementation Options
Lab 6: Designing for Performance
Power Estimation (Optional)
Lab 7: FPGA Editor Demo (Optional)
ChipScope Pro Analyzer (Optional)
Lab 8: ChipScope Pro Analyzer (Optional)
Course Summary
Labs
Lab 1 - CORE Generator Software System: Create a core, instantiate the core into VHDL or Verilog source code, and run behavioral simulation.
Lab 2 - Designing Clock Resources: Use the Clocking Wizard to configure the DCMs and global clock buffer resources.
Lab 3 - Synthesis Techniques: Experiment with different synthesis options and view the results. Versions of this lab are available for Synplicity Synplify Pro, Precision RTL, and Xilinx XST software.
Lab 4 - Review of Global Timing Constraints: Use the Constraints Editor to enter global timing constraints.
Lab 5 - Achieving Timing Closure: Review timing reports and enter path-specific timing constraints to meet performance goals.
Lab 6 - Designing for Performance: Improve performance and maximize results solely with implementation options.
Lab 7 - FPGA Editor Demo: Use the FPGA Editor to view a design and add a probe to an internal net.
Lab 8 - ChipScope Pro Analyzer: Add an internal logic analyzer to a design to perform real-time debugging.
Prerequisites
- Fundamentals of FPGA Design course or equivalent knowledge of:
- FPGA architecture features
- Xilinx implementation software flow and implementation options
- Reading timing reports
- Basic FPGA design techniques
- Global timing constraints
- Constraints Editor
- Intermediate HDL knowledge (VHDL or Verilog)
- Solid digital design background
Scheduled Sessions
Education Investment Options
| Course & Basic Follow-on Coaching |
$1,599 |
REGISTER |
| Course & Comprehensive Follow-on Coaching |
$2,199 |
REGISTER |
| Course Only |
$1,399 |
REGISTER |
| Basic Coaching ala Carte |
Not currently offered |
REGISTER |
| S3 Board & 1 hour support |
$399 |
REGISTER |
| V4 Board & 1 hour support |
$599 |
REGISTER |
| V5 Board & 1 hour support |
$1,399 |
REGISTER |
Basic follow-on coaching includes 2 hours (max 4 calls)
Comprehensive follow-on coaching includes 8 hours (max 12 calls)
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