Bottom Line Technologies Inc.   FPGA, Product, and System Design for Commercial, 
				Industrial, Military, and Aerospace Markets.  BLT designs incorporate FPGAs, DSP, PCI, and often FW
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    Design Techniques for Lower Cost
    This course will appeal to engineers who have an interest in developing low-cost products, particularly in high-volume markets. The course and exercises cover several different design techniques, which will be interesting and challenging for any digital designer regardless of the final application.

    Level
    Fundamental

    Duration
    1 Day

    Who Should Attend
    Engineers wanting to develop low-cost products, particularly in high-volume markets, and product designers who need to accurately estimate the size of devices required to implement products to predict costs without requiring the actual design to be implemented

    Software Tools
    No software is needed for this workshop

    Skills Gained
    After completing this comprehensive training, you will have the necessary skills to:
  • Describe the features of the Spartan-3 and Spartan-IIE devices
  • Accurately estimate design size to aid in predicting product costs
  • Apply design techniques that result in low-cost implementations
  • Explore creative ways to use the FPGA memory resources to reduce design costs

    Course Outline
  • What is an FPGA?
  • Spartan Family
  • CLBs, Slices and BRAM
  • Multiplexers
  • Flip-Flop Controls
  • Synchronous Timing vs. Asynchronous Timing
  • Digital Clock Managers
  • Dedicated Carry Logic
  • Counters
  • Wired Carry Gates
  • Block Memory
  • Distributed RAM
  • FIFO
  • Dual Port Memory
  • PicoBlaze™ Microcontroller Processor
  • State Machines
  • Design Challenges

    Labs
  • Exercise 1: Exploring the Slice
  • Exercise 2: Logic Levels
  • Exercise 3: Dedicated Multiplexers
  • Exercise 4: Performance by Design
  • Exercise 5: Clocks
  • Exercise 6: Counters
  • Exercise 7: Aspect Ratios
  • Exercise 8: Replacing Logic with Block RAM
  • Exercise 9: Distributed RAM
  • Exercise 10: Essence of FIFO
  • Exercise 11: Delay
  • Exercise 12: PicoBlaze Microprocessor
  • Exercise 13: State Machines


  • Prerequisites
    • An understanding of digital logic design and the concept of an FPGA
    • An appreciation of VHDL and CAE design flows is beneficial, but not vital


    No Scheduled Sessions
    Contact Bottom Line Technologies for more information

    Education Investment Options
    Course & Basic Follow-on Coaching $749 REGISTER
    Course & Comprehensive Follow-on Coaching $1,199 REGISTER
    Course Only $599 REGISTER
    Basic Coaching ala Carte Not currently offered REGISTER
    S3 Board & 1 hour support $399 REGISTER
    V4 Board & 1 hour support $599 REGISTER
    V5 Board & 1 hour support $1,399 REGISTER
  • Basic follow-on coaching includes 1 hour (max 2 calls)
  • Comprehensive follow-on coaching includes 4 hours (max 6 calls)
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