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Xilinx Training Courses
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Download Course Flyer (~1 MB)
Download Full Course Catalog (~4 MB)
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FPGA Design Courses
Fundamentals of FPGA Design
This course covers ISE 9.1i features, such as the Architecture Wizard and the Floorplan Editor. Other topics include design planning, implementation options, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.
Designing for Performance
Create more efficient designs that fit in a smaller FPGA or lower speed grade to reducing system costs. Master the tools and the design methodologies presented in this course to create your design faster, shorten your development time, and lower development costs.
Advanced FPGA Implementation
Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE™ 9.1i tool suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover Synplicity’s Synplify and the Xilinx XST tools. This course requires the Fundamentals of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months’ design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE software 9.1i tools and the Virtex™-4 FPGAs.
Designing with PlanAhead
Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software tool. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.
Designing with the Virtex-4 FPGA Family
Learn how to utilize Virtex™-4 FPGA architectural resources effectively. This course includes an overview of the Virtex-4 FPGA; the Digital Clock Manager (DCM) and Phase-Matched Clock Divider (PMCD); global and regional clocking techniques, memory and FIFO; and source synchronous resources. A combination of modules and labs allow for practical hands-on application of the principles taught in this course.
Designing with the Virtex-5 FPGA Family
Interested in learning how to utilize Virtex™-5 FPGA architectural resources effectively? Targeted towards experienced Xilinx users who have already completed
Fundamentals of FPGA Design and
Designing
for Performance
and have a comprehensive knowledge of Virtex-4 FPGAs, this course focuses on understanding as well as designing into
several of the new and enhanced resources found in our newest device.
Design Techniques for Lower Cost
This course appeals to engineers who have an interest in developing low-cost products, particularly in high-volume markets. The course and exercises cover several different design techniques, which will be interesting and challenging for any digital designer regardless of the final application.
Introduction to VHDL
This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course. In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.
Advanced VHDL
Increase your VHDL proficiency by learning advanced techniques that help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL. The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.
Introduction to Verilog
This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.
TMRTool
Incoming students with little knowledge of SEU/SET considerations who complete this one-day course will get a thorough overview of how these risks affect technology in general and FPGAs in particular. This introduction to the Xilinx TMR (XTMR) solution addresses designs that require Triple Module Redundancy and provides hands-on experience, allowing you to evaluate TMR’s timing impact, as well as area and pinout considerations. You will also perform design verification to ensure functional integrity for pre- and post-TMR circuits. The XTMR solution incorporates XilinxTraining_TMRTool, a proprietary software application that offers total control and flexibility for the TMR process for Xilinx FPGAs.
ISE Design Entry
In this course you will learn about project structure, process windows, various ISE™ software design flows, and Xilinx Synthesis Technology (XST). You will examine XST synthesis and use the XST constraints file in the Project Navigator GUI. You will learn about the Engineering Capture System (ECS) and the StateCAD and ISE Simulator tools.
Connectivity Design Courses
LogiCORE PCI System Design
Learn the tips and tricks of PCI design in this two-day course which provides an introduction to basic PCI concepts and architecture as well as intensive training on designing with the PCI core for Xilinx. This course emphasizes and illustrates how PCI transactions take place and gives you an overview of Xilinx PCI solutions. You will learn the basics of Xilinx PCI cores including PCI 64/66 and PCI 32. You will also learn design concepts and basic verification strategies for creating a PCI system design. The labs cover the basic transaction analysis using the ModelSim simulator and the general design flow, from core to verification using ISE 9.1i.
LogiCORE PCI-X System Design
This course focuses on the PCI-X Addendum to the PCI Local Bus Specification and provides a detailed examination of the PCI-X LogiCORE™ solution. This course will help digital designers interface the PCI-X LogiCORE solution to a typical user application to create a flexible PCI-X system design.
LogiCORE PCI Express System Design
Attending the Designing a LogiCORE PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express® core in your applications. This course focuses on the implementation of a Xilinx PCI Express system with supporting logic and example designs. With this experience, you can improve your time to market with your PCIe core design.
Multi-Gigabit Serial I/O Design
Learn how to employ RocketIO™ GTP serial transceivers in your Virtex™-5 LXT FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as CRC, 8B/10B encoding, channel bonding, clock correction, and comma detection. Additional highlighted topics include use of the Architecture Wizard and synthesis and implementation considerations. This course balances lecture modules and practical hands-on labs.
Ethernet MAC Controller Design
After completing this course, you will be familiar with the various Xilinx solutions offering Ethernet connectivity. You will learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. You will also perform simulations and learn to assess hardware design considerations and software development requirements.
Signal Integrity for High-Speed Memory and Processor I/O
Learn how signal integrity techniques are applicable to high-speed interfaces between Xilinx FPGAs and semiconductor memories. This course will teach you about high-speed bus and clock design, including transmission line termination, loading, and jitter. You will work with IBIS models, complete simulations using CAD packages, and manage PCB effects and on-chip termination. This course includes both lecture modules and practical hands-on labs.
CPLD Design Courses
Fundamentals of CPLD Design
This comprehensive course provides you with an introduction to designing with Xilinx CPLDs by using the ISE™ series software tools. You will learn the basics of ISE software flow and how to interpret CPLD reports for optimum performance designs. This course covers ISE features such as the Constraints Editor and PACE. Other topics include design planning, implementation options, and global timing constraints. You will ultimately configure a CPLD demo board by using Xilinx configuration software.
Designing for Performance for CPLDs
Designing for Performance for CPLDs is an intermediate-level course that provides a comprehensive overview of the CPLD software flow. By applying the techniques presented in this course, you will be able to enhance design performance and make the best possible use of Xilinx CPLD architectures. This course uses the ISE™ 9.1 software, including the Constraints Editor and Timing Analyzer. Other topics include understanding the CPLD logic engine, estimating power, and fitting difficult designs.
DSP Design Courses
DSP Implementation Techniques for Xilinx FPGAs
This course will show you how to take advantage of Xilinx FPGA architecture, including the Virtex™-4 FPGA, to effectively implement DSP algorithms. The techniques also demonstrate which system-level decisions have the greatest impact on the implementation process and product costs.
DSP Design Using System Generator
This course allows you to explore the System Generator tool and gain the expertise required to develop advanced, low-cost DSP designs. This intermediate course focuses on using System Generator for DSP, design implementation tools, and hardware-in-the-loop verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification with Xilinx FPGAs
Introduction to AccelDSP
Learn how to synthesize an algorithm written in the language of MATLAB® software into a design that is optimized for a Xilinx FPGA. Find out how to make coding changes in MATLAB® software that improve area and performance. Use the floating- to fixed-point and design exploration features of the AccelDSP™ synthesis tool to achieve maximum results. Merge a synthesized MATLAB® software block into a larger HDL design or System Generator design.
Embedded Design Courses
Embedded Systems Development
Xilinx Field Programmable Gate Array (FPGA) provides a new level of system design capabilities through its MicroBlaze™ soft processor and hard core PowerPC® processor as well as silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The basic features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC processor are also included in the lectures and labs. These hands-on labs are plentiful and provide personal experience with the development, debugging, and simulation of an embedded system.
Advanced Embedded Systems Development
Advanced Features and Techniques of Embedded Systems Development provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Embedded Development Kit (EDK). This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system.
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