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Introduction to VHDL

This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lecture with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Level
Fundamental to Intermediate

Duration
3 Days

Who Should Attend
Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs

Software Tools

ISE� 9.1i

Xilinx ISIM Simulator

Synplicity Synplify Pro

Skills Gained
After completing this comprehensive training, you will have the necessary skills to:

Write RTL VHDL code for synthesis

Write VHDL testbenches for simulation

Create Finite State Machines (FSMs) by using VHDL

Target and optimize Xilinx FPGAs by using VHDL

Create RAM and ROM data structures

Use VHDL scalar and composite data types

Run a simulation by using VITAL libraries

Use VHDL Text I/O during simulation

Create and manage designs within the ISE? software design environment

Course Outline
Day 1

Course Agenda

Hardware Modeling Overview

VHDL Language Concepts

Lab 1: Building Hierarchy

Introduction to Testbenches

Lab 2: VHDL Simulation and RTL Verification

Signals and Data Types

VHDL Operators and Expressions

Lab 3: Memory and Record

Day 2

Lab 4: n-bit Binary Counter and RTL Verification ! Controlled Operation Statements

Lab 5: Comparator

Finite State Machines

Lab 6: Arithmetic Logic Unit

Behavioral to RTL Coding

Lab 7: State Machines

Day 3

Targeting Xilinx FPGAs

VITAL: VHDL Initiative toward ASIC Libraries

Lab 8: Calculator

Functions and Procedures

Advanced Process Statements

Lab 9: Text I/O

Labs
The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that you will verify in simulation.

Prerequisites

Basic digital design knowledge

Scheduled Sessions

Parsippany,NJ - TBD

7/22/2009 through 7/24/2009

Education Investment Options

Course & Basic Follow-on Coaching	$2,300	REGISTER
Course & Comprehensive Follow-on Coaching	$2,900	REGISTER
Course Only	$2,100	REGISTER
Course Only	21 Training Credits	REGISTER
Basic Coaching ala Carte	Not currently offered	REGISTER
S3 Board & 1 hour support	$450	REGISTER
V4 Board & 1 hour support	$800	REGISTER
V5 Board & 1 hour support	$1,900	REGISTER

Basic follow-on coaching includes 2 hours (max 4 calls)

Comprehensive follow-on coaching includes 8 hours (max 12 calls)