Bottom Line Technologies
HOME | SITE MAP | CONTACT

Subscribe to eNewsletter
Email:
  • Training
  • |
  • Design Services
  • |
  • Industries
  • |
  • Technologies
  • |
  • Philosophy

Training Home
Training Courses
• FPGA
• Connectivity
• CPLD
• DSP
• Embedded Design
BLT Stimulus Package
Follow-on Coaching

Related Links
Public Class Schedule
Private Classes
Training Facilities
Training Policies
Xilinx Design Services
HOME > Services> Training> Training Courses>

DSP Design Using System Generator

This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware-in-the-loop verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.

Level
Intermediate

Duration
2 Days

Who Should Attend
System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using MathWorks MATLAB and Simulink and want to use Xilinx System Generator for DSP design

Software Tools
  • Xilinx ISE™ 9.1i SP2 with IP update 1
  • Xilinx System Generator 9.1
  • MathWorks MATLAB with Simulink R2006b

    Skills Gained
    After completing this comprehensive training, you will have the necessary skills to:
  • Describe the System Generator design flow for implementing DSP functions
  • Identify Xilinx FPGA capabilities and implement a design from algorithm concept to hardware simulation
  • List various low-level and high-level functional blocks available in System Generator
  • Recognize that hardware may be required for high-level abstraction
  • Identify the high-level blocks available for FIR and FFT designs
  • Perform hardware-in-the-loop and improve productivity
  • Design a multiple clock-based System Generator system
  • Employ various design techniques for improving system performance

    Course Outline
    Day 1
  • Introduction to System Generator
  • Simulink Basics
  • Lab 1: Using Simulink
  • Basic Xilinx Design Capture
  • Lab 2: Getting Started with Xilinx System Generator
  • Signal Routing
  • Lab 3: Signal Routing
  • Implementing System Control
  • Lab 4: Implementing System Control

  • Day 2
  • Multi-Rate Systems
  • Lab 5: Designing a MAC-based FIR
  • Filter Design
  • Lab 6: Designing a FIR Filter Using the FIR Compiler Block or DAFIR Block
  • Memories
  • Lab 7: Designing with Shared Memories
  • Achieving Higher Performance
  • Lab 8: Improving Design Performance


  • Labs
  • Lab 1: Using Simulink – Learn how to use Simulink toolbox blocks and design a system. Understand the effect sampling rate.
  • Lab 2: Getting Started with Xilinx System Generator – Design a DSP48-based (ML403) or Multiply and Accumulator block-based (SP3E) 12 x 8 MAC. Perform hardware-in-the-loop verification targeting an ML403 and/or Spartan™-3E FPGA starter board.
  • Lab 3: Signal Routing – Design padding and unpadding logic using signal routing blocks.
  • Lab 4: Implementing System Control – Design an address generator circuit using blocks and Mcode.
  • Lab 5: Designing a MAC-based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware-in-the-loop using an ML403 and/or Spartan-3E FPGA starter board.
  • Lab 6: Designing a FIR Filter Using the FIR Compiler Block or DAFIR Block – Design a bandpass FIR filter using the FIR Compiler block (ML403) or DAFIR block (SP3E) to demonstrate increased productivity. Verify the design through hardware-in-the-loop using an ML403 and/or Spartan-3E FPGA starter board.
  • Lab 7: Designing with Shared Memories – Learn to use multiple System Generator blocks to design and implement a multi-clock domain system. Verify the design in hardware using an ML403 and/or Spartan-3E FPGA starter board.
  • Lab 8: Improving Design Performance – Use the Timing Analyzer block and other techniques to improve system performance.


  • Prerequisites
    • Experience with MATLAB and Simulink
    • Basic understanding of sampling theory

    Scheduled Sessions
    Parsippany,NJ - TBD 7/30/2009 through 7/31/2009
    Columbia,MD - Genesis Mid Atlantic 8/6/2009 through 8/7/2009
    Rochester,NY - Avnet 8/27/2009 through 8/28/2009
    Plymouth Meeting,PA - SpringHill Suites 9/3/2009 through 9/4/2009

    Education Investment Options
    Course & Basic Follow-on Coaching $1,600 REGISTER
    Course & Comprehensive Follow-on Coaching $2,200 REGISTER
    Course Only $1,400 REGISTER
    Course Only 14 Training Credits REGISTER
    Basic Coaching ala Carte Not currently offered REGISTER
    S3 Board & 1 hour support $450 REGISTER
    V4 Board & 1 hour support $800 REGISTER
    V5 Board & 1 hour support $1,900 REGISTER
  • Basic follow-on coaching includes 2 hours (max 4 calls)
  • Comprehensive follow-on coaching includes 8 hours (max 12 calls)
    • Contact
    • |
    • Company
    • |
    • Careers
    • |
    • Outsourcing
    • |
    • Resources
    • |
    • Legal
    Copyright (c) 2009 Bottom Line Technologies Inc. All rights reserved. Version 5.70 - 2009-05-28 15:45