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Designing with the Virtex-5 FPGA Family

Interested in learning how to utilize Virtex�-5 FPGA architectural resources effectively? Targeted towards experienced Xilinx users who have already completed Fundamentals of FPGA Design and Designing for Performance and have a comprehensive knowledge of Virtex-4 FPGAs, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device.

Topics covered include a Virtex-5 FPGA overview, new CLB, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources. Additionally, the new resources available in the LXT platform (EMAC, PCI Express, and GTP) are discussed. A combination of modules and labs allow for practical hands-on application of the principles taught.

Note: Recorded e-Learning modules will also be available in North America. For all other regions, only the recorded e-Learning modules will be available. Also note that the initial course material covers the Virtex-5 LX and LXT FPGA platforms only. Future revisions will include additional platforms as they become available.

Level
Intermediate

Duration
1 Day

Who Should Attend
For those who have taken the Fundamentals of FPGA Design and Designing for Performance courses. A comprehensive knowledge of the Virtex-4 family architecture is also required. This material should be considered a Virtex-5 FPGA update course from the Virtex-4 FPGA family.

Software Tools

Xilinx ISE� 9.1i

Skills Gained
After completing this comprehensive training, you will have the necessary skills to:

Describe the 6-input LUT of the Virtex-5 FPGA

Specify the CLB arrangement in the Virtex-5 FPGA

Define the block RAM resources of the Virtex-5 FPGA

Differentiate the arithmetic resources of the DSP48E slice in the Virtex-5 FPGA

Identify the clocking resources of the Virtex-5 FPGA

Describe the new features of the Virtex-5 LXT FPGA

Course Outline

Introduction

Virtex-5 FPGA Overview

CLB Resources

Clocking Resources

Lab 1: Clocking Resources

I/O Resources

Memory Resources

XtremeDSP Technology Resources

Lab 2: DSP48E Resources

Virtex-5 LXT FPGA Overview

Labs

Lab 1 - Clocking Resources: In this lab, you will use the Architecture Wizard to create a PLL core for instantiation in your design. You will then simulate and verify the PLL core.

Lab 2 - DSP48E Resources: In this lab, you will create a MACC and a loadable MACC by using the XtremeDSP technology (DSP48E) resource through the CORE Generator™ software. You will then compare the OPMODEs chosen by the CORE Generator software with the expected values.

Prerequisites

Fundamentals of FPGA Design course
Designing for Performance course
Designing with the Virtex-4 FPGA Family course or comprehensive knowledge of the Virtex-4 FPGA

Scheduled Sessions

Parsippany,NJ - TBD

7/21/2009 through 7/21/2009

Education Investment Options

Course & Basic Follow-on Coaching	$900	REGISTER
Course & Comprehensive Follow-on Coaching	$1,500	REGISTER
Course Only	$700	REGISTER
Course Only	7 Training Credits	REGISTER
Basic Coaching ala Carte	Not currently offered	REGISTER
S3 Board & 1 hour support	$450	REGISTER
V4 Board & 1 hour support	$800	REGISTER
V5 Board & 1 hour support	$1,900	REGISTER

Basic follow-on coaching includes 2 hours (max 4 calls)

Comprehensive follow-on coaching includes 8 hours (max 12 calls)