Designing With the PlanAhead Analysis and Design Tool

Course Description

Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.

Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool.

Advanced topics include: synthesis and project tips, design analysis, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope™ Pro tool, and design preservation with partitions. p>

Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.

Release Date

2010

Training Duration

3 days

Who Should Attend?

FPGA designers, system architects, and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.

Prerequisites

• Essentials of FPGA Design or equivalent knowledge of the FPGA architecture and the Xilinx ISE® software flow
• Designing for Performance recommended

Software Tools

• Xilinx ISE Design Suite: Logic or System Edition 12.1

Hardware

• Architecture: Virtex®-6 FPGA*
• Demo board: None*

* This course focuses on the Virtex-6 architecture. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Use the basic and most advanced features of the PlanAhead tool
• Import designs into the PlanAhead tool project environment
• Assign I/O pins and clock logic
• Run DRC and SSN noise analysis
• Integrate IP with the PlanAhead tool
• Import HDL sources, elaborate, and analyze the RTL netlist
• Implement the design with different implementation strategies
• Analyze design statistics and timing
• Use the PlanAhead tool integrated with the ISE tool Project Navigator environment
• Apply the hierarchical viewer and timing report information to make the best area constraints
• Group the best logic into Pblocks
• Import HDL sources, elaborate, and analyze an RTL netlist
• Implement the design with different implementation strategies
• Analyze design statistics, connectivity, timing, placement, and timing critical paths
• Insert ChipScope Pro tool debug cores
• Floorplan the design to improve performance and preserve successful implementation results
• Make placement constraints for dedicated hardware resources

Course Outline

Day 1

• PlanAhead Tool Benefits and Features Overview
• PlanAhead Tool Project Manager
• Lab 1: Getting Started with the PlanAhead Tool
• I/O Pin and Clock Planning
• Lab 2: Assigning I/O Pins
• CORE Generator Tool Integration
• Lab 3: CORE Generator Tool Integration
• Project Navigator Integration

Day 2

• PlanAhead Software Review
• Lab 4:PlanAhead Software Review
• RTL Development and Analysis
• Lab 5: RTL Development and Analysis
• Placing Dedicated Resources
• Lab 6:Placing Dedicated Resources

Day 3

• Pblocks
• Floorplanning Techniques
• Lab 7:Design Analysis and Floorplanning for Performance
• Design Preservation with Partitions
• Lab 8:Leveraging Design Preservation for Predictable Results
• Debugging with the ChipScope Tool
• Lab 9: Debugging with the ChipScope Tool

Lab Descriptions

Note: All labs in this course are also available as self-guided tutorials, which are packaged with the PlanAhead software.

• Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.
• Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.
• Lab 3: CORE Generator Tool Integration – Illustrates the integration of the CORE Generator tool with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog, and view the generated core with the Schematic viewer.
• Lab 4: PlanAhead Software Review – Illustrates the steps you take to import source HDL files into the PlanAhead tool and synthesize, implement, and analyze the results. Also introduces the PlanAhead tool environment and views.
• Lab 5: RTL Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations, RTL power estimations, and run an RTL Design Rule Check (DRC).
• Lab 6: Placing Dedicated Resources – Introduces the methods for assigning location constraints to dedicated hardware resources. Demonstrates how to assign dedicated clocking resources, work with multi-function I/O pins, and complete a SSN noise analysis.
• Lab 7: Design Analysis and Floorplanning for Performance – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.
• Lab 8: Leveraging Design Preservation for Predictable Results – Introduces the use of partitions to maintain successful implementation results.
• Lab 9: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope Pro tool, cores, and Set Up ChipScope Wizard.

Customer Reviews 

• The instructor did a good job and the class was fun. There was lots of student involvement, which was good.
  
  
  
• Overall this was a very good experience. The instructor was very knowledgable, and paced the lectures very well. The Lab content was very appropriate and well planned.
  
  
  
• Good course. I learned a lot.