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HOME > Services> Training> Training Courses>

Designing with PlanAhead

Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software tool. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.

Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead software. This course is supplemented with instructor-led presentations and demos.

Level
Intermediate

Duration
2 Days

Who Should Attend
FPGA designers, system architects, and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.

Software Tools
  • Xilinx ISE 9.1i
  • PlanAhead 9.1.2

    Skills Gained
    After completing this comprehensive training, you will have the necessary skills to:
  • Import designs into the PlanAhead software project environment
  • Analyze design statistics, connectivity, timing, and placement results
  • Run the Design Rule Checker (DRC) and Weighted Average Simultaneous Switching Output (WASSO) analysis
  • Partition and floorplan designs
  • Run ExploreAhead to try multiple implementation strategies
  • Import and analyze the implementation results to improve the floorplan
  • Floorplan to improve performance and consistency
  • Use block-based design and create and reuse module-level IP
  • Use PinAhead to import, define and assign I/O pins for the design

    Course Outline
    Day 1
  • Course Overview
  • Lab 1: Getting Started with PlanAhead
  • Design Analysis and Exploration
  • Lab 2: Design Analysis and Exploration
  • Design Partitioning and Top-Level Floorplanning
  • Lab 3: Design Partitioning and Top-Level Floorplanning
  • Implementing a Floorplanned Design
  • Lab 4: Implementation

  • Day 2
  • Floorplanning Techniques
  • Lab 5: Floorplanning
  • Tuning a Floorplan for Performance
  • Lab 6: Floorplan Tuning
  • Block-Based Design and IP Reuse
  • Lab 7: Block-Based Design and IP Reuse
  • I/O Pin Assignment
  • Lab 8: I/O Pin Assignment
  • Floorplanning Strategies
  • Course Summary


  • Labs
  • Lab 1: Getting Started with PlanAhead – Illustrates the steps you take to import a synthesized design into the PlanAhead software so that you can begin floorplanning. Also introduces the PlanAhead software environment and views.
  • Lab 2: Design Analysis and Exploration – Introduces the analysis features of the PlanAhead software that enable early detection of potential design issues, alternate device selection, initial floorplanning direction, and post-implementation exploration.
  • Lab 3: Design Partitioning and Top-Level Floorplanning – Introduces the concept of floorplanning. By using automated partitioning tools, you will create a top-level floorplan and experiment with sizing and shaping Pblocks based on resources assigned to them.
  • Lab 4: Implementation – Introduces the integration of the ISE software implementation tools with the PlanAhead software. Also introduces the ExploreAhead tool for queuing multiple ISE software runs with varying strategies.
  • Lab 5: Floorplanning – Describes how to analyze implementation results and to use that information to generate a floorplan aimed at increasing design performance.
  • Lab 6: Floorplan Tuning – Introduces techniques to help close on timing targets consistently.
  • Lab 7: Block-Based Design and IP Reuse – Describes the steps to implement a block-based methodology that includes the creation and reuse of an IP module.
  • Lab 8: I/O Pin Assignment – Introduces the PinAhead environment for performing I/O pin assignment


  • Prerequisites
    • Fundamentals of FPGA Design course or equivalent knowledge
    • Designing for Performance course or equivalent knowledge

    Scheduled Sessions
    Plymouth Meeting,PA - SpringHill Suites 6/25/2009 through 6/26/2009
    Rochester,NY - Avnet 7/9/2009 through 7/10/2009
    Parsippany,NJ - TBD 8/6/2009 through 8/7/2009
    Columbia,MD - Genesis Mid Atlantic 8/27/2009 through 8/28/2009

    Education Investment Options
    Course & Basic Follow-on Coaching $1,600 REGISTER
    Course & Comprehensive Follow-on Coaching $2,200 REGISTER
    Course Only $1,400 REGISTER
    Course Only 14 Training Credits REGISTER
    Basic Coaching ala Carte Not currently offered REGISTER
    S3 Board & 1 hour support $450 REGISTER
    V4 Board & 1 hour support $800 REGISTER
    V5 Board & 1 hour support $1,900 REGISTER
  • Basic follow-on coaching includes 2 hours (max 4 calls)
  • Comprehensive follow-on coaching includes 8 hours (max 12 calls)
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    Copyright (c) 2009 Bottom Line Technologies Inc. All rights reserved. Version 5.70 - 2009-05-28 15:45