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LogiCORE PCI Express System Design

By learning PCI Express core protocol fundamentals, designers will gain a working knowledge of how PCI Express can be used in their systems. This course focuses on the PCI Express protocol subjects that designers, using the Xilinx PCI Express core, should understand to complete their designs faster and more easily. Students will also be introduced to each Xilinx PCI Express core product and will gain intimate knowledge of how the PCI Express core operates.

Level
Intermediate

Duration
2 Days

Who Should Attend

Hardware designers who want to create applications using Xilinx IP cores for PCI Express

Software engineers who want to understand the deeper workings of the Xilinx LogiCORE PCI Express solution

System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications

Software Tools

Xilinx ISE 9.2i

ISIM 9.2i

ChipScopePro9.2i

Skills Gained
After completing this comprehensive training, you will have the necessary skills to:

Effectively use the Xilinx PCI Express cores in your own design environments

Select the appropriate PCI solution for a specific application

Identify how PCI Express specification requirements apply to using Xilinx PCI Express cores

Course Outline
Day 1

Course Introduction

Review of the PCIe System Architecture and Protocol

PCIe and CORE Generator

Lab 1: Constructing the PCIe Core

Simulating a PCIe Design

Connecting Logic to the Core – Local Link

Lab 2a: Downstream Port Model Simulation

Designing the Endpoint Application

Lab 2b: Pseudo-Transactional Modeling

Day 2

Lab 3: Implementing the Design

Compliance and Debugging

Lab 4: Debugging the PCIe Core with the ChipScope Pro Tools

Errors and Interrupts

Host Side –Applications and Drivers

Note: Lab 4 is currently only offered at Xilinx factory taught classes.

Labs

Lab 1: Constructing the PCIe Core: Familiarizes you with all the necessary flow of the Xilinx CORE Generator™ software for generating a Xilinx LogiCORE™ Endpoint Block Plus IP. You will select appropriate parameters for the CORE Generator tool and create the PCIe core used throughout the labs

Labs 2a&b: Simulating the PCIe Core: Provides an overview of simulating the core using the ISIM tool. You will observe and capture the effects of link training and write packets to the endpoint application during the Downstream Port Model simulation. This data will be played back during a transactional module simulation lab.

Lab 3: Implementing the Design: Familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream.

Lab 4: Debugging Strategies: Using a traffic simulator, you will use the ChipScope™ Pro tools to monitor the behavior of the core and the endpoint application for proper operation.

Note: Lab 4 is currently only offered at Xilinx factory taught classes.

Prerequisites

Comprehensive understanding of the PCIe protocol (2 hour review included)
Solid knowledge of Verilog or VHDL
Solid experience with commonly used simulation tools such as Mentor Graphics ModelSim or ISIM
Basic knowledge of Xilinx ISE� software
Designing for Performance and Designing with Multi-Gigabit Serial I/O are recommended

Scheduled Sessions

Plymouth Meeting,PA - SpringHill Suites	6/9/2009 through 6/10/2009
Columbia,MD - Genesis Mid Atlantic	6/16/2009 through 6/17/2009
Parsippany,NJ - TBD	9/1/2009 through 9/2/2009
Columbia,MD - Genesis Mid Atlantic	9/8/2009 through 9/9/2009
Rochester,NY - Avnet	9/22/2009 through 9/23/2009

Education Investment Options

Course & Basic Follow-on Coaching	$1,600	REGISTER
Course & Comprehensive Follow-on Coaching	$2,200	REGISTER
Course Only	$1,400	REGISTER
Course Only	14 Training Credits	REGISTER
Basic Coaching ala Carte	Not currently offered	REGISTER
S3 Board & 1 hour support	$450	REGISTER
V4 Board & 1 hour support	$800	REGISTER
V5 Board & 1 hour support	$1,900	REGISTER

Basic follow-on coaching includes 2 hours (max 4 calls)

Comprehensive follow-on coaching includes 8 hours (max 12 calls)