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Minimizing Your Design Time with ChipScopePro

As FPGA designs become increasingly more complex, designers are searching to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for debug and verification. This one-day course will show you effective ways to debug logic and high-speed designs�thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope™ Pro tools can address advanced verification and debugging challenges.

Level
Intermediate

Duration
1 Day

Who Should Attend
Logic, high-speed, and embedded designers looking to minimize debug and verification time.

Software Tools

Xilinx ISE 9.2i

ChipScope Pro 9.2i

Skills Gained
After completing this comprehensive training, you will have the necessary skills to:

Maximize ChipScope Pro tool core performance

Minimize negative timing impacts on a design

Use techniques that enhance and extend the capabilities of the ChipScope Pro tools

Enable and identify the advantages of remote debugging

Course Outline

Agenda and Introduction

Lab 1: Adding the ILA Core to an Existing Design and/or Adding the ILA and VIO Cores for Remote Monitoring and Control Timing Implications

Demo: Minimizing ILA Core Impact with the PlanAhead Software

Tips and Tricks

Lab 2: Tips and Tricks

Remote Debug

Labs

Lab 1 - Adding the ILA Core to an Existing Design : You will use the Core Inserter tool flow for adding the ChipScope Pro tool ILA cores into a design to rapidly locate and solve a simple logic problem.

Lab 2 - Adding the ILA and VIO Cores for Remote Monitoring and Control : You will instantiate ICON, ILA, and VIO cores into a VHDL or Verilog design and practice monitoring signals of interest and externally driving select control signals.

Lab 3 - Tips and Tricks : This lab demonstrates the flexibility of the ChipScope Pro tool solution as you explore data qualification, cross-clock domain analysis, and oversampling techniques.

Lab 4 - Enabling Remote Debug*: This lab demonstrates how the ChipScope Pro tools can be used across a network. You will connect to another team�s board, download your bitstream, and remotely monitor the other team�s board on your machine.

Prerequisites

FPGA design experience or completion of the Xilinx Fundamentals of FPGA Design course

FPGA architecture features
Xilinx implementation software flow and implementation options
Reading timing reports
Basic FPGA design techniques
Global timing constraints
Constraints Editor

Intermediate HDL knowledge (VHDL or Verilog)
Solid digital design background

Scheduled Sessions

Columbia,MD - Genesis Mid Atlantic	6/12/2009 through 6/12/2009
Rochester,NY - Avnet	7/31/2009 through 7/31/2009
Parsippany,NJ - TBD	9/11/2009 through 9/11/2009
Columbia,MD - Genesis Mid Atlantic	9/18/2009 through 9/18/2009
Plymouth Meeting,PA - SpringHill Suites	9/25/2009 through 9/25/2009

Education Investment Options

Course & Basic Follow-on Coaching	$900	REGISTER
Course & Comprehensive Follow-on Coaching	$1,500	REGISTER
Course Only	$700	REGISTER
Course Only	7 Training Credits	REGISTER
Basic Coaching ala Carte	Not currently offered	REGISTER
S3 Board & 1 hour support	$450	REGISTER
V4 Board & 1 hour support	$800	REGISTER
V5 Board & 1 hour support	$1,900	REGISTER

Basic follow-on coaching includes 2 hours (max 4 calls)

Comprehensive follow-on coaching includes 8 hours (max 12 calls)