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Advanced FPGA Implementation

Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE� 10.1i tool suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover Xilinx XST tools. This course requires the Fundamentals of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months� design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE software 10.1i tools and the Virtex�-5 FPGAs.

Level
Advanced

Duration
2 Days

Who Should Attend
Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity

Software Tools

Xilinx ISE 10.1i

Skills Gained
After completing this training, you will have the necessary skills to:

Implement designs via the Tcl command line

Create and edit timing constraints in the User Constraint File (UCF) file

Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfaces

Preserve design results by using SmartGuide� technology or partitions

Use the Floorplan Editor or Pinout and Area Constraints Editor (PACE) to create area constraints

Change signals of interest in the ChipScope Pro tool for board-level debugging using the FPGA Editor

Course Outline

Introduction

Lab 1: Achieving Timing Closure and Review of Global Timing Constraints

Tcl Scripting

Lab 2: Tcl Scripting

UCF Editing

Lab 3: UCF

Advanced I/O Timing

Lab 4: Advanced I/O Timing

SmartCompile Design Preservation Techniques

Lab 5: SmartCompile Technology

Floorplanning Effective Layout

Lab 6: Floorplanning

FPGA Editor: Viewing and Editing a Routed Design

Lab 7: FPGA Editor

Labs

Lab 1: Achieving Timing Closure and Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.

Lab 2: Tcl Scripting – Write ISE tool control commands in a Tcl script file to implement the design. Then modify program switches to obtain the greatest possible performance from the design.

Lab 3: UCF – Write constraints directly into a UCF file to guide the performance results of implementation.

Lab 4: Advanced I/O Timing – Compose timing constraints for I/O interface. Analyze the timing failures and determine changes to correct the timing issues. Modify the design to fix timing failures.

Lab 5: SmartCompile Technology – Utilize SmartGuide technology and partitions to preserve the timing results from one iteration to the next.

Lab 6: Floorplanning – Implement a design using floorlplanned constraints to enhance the timing results over a design without floorplanning.

Lab 7: FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.

Prerequisites

Fundamentals of FPGA Design course or equivalent knowledge
Designing for Performance course or equivalent knowledge
Intermediate HDL knowledge (VHDL or Verilog) is strongly recommended
Solid digital design background
At least six months' design experience with Xilinx tools and FPGAs is strongly recommended

Scheduled Sessions

Plymouth Meeting,PA - SpringHill Suites	6/23/2009 through 6/24/2009
Rochester,NY - Avnet	7/7/2009 through 7/8/2009
Parsippany,NJ - TBD	8/4/2009 through 8/5/2009
Columbia,MD - Genesis Mid Atlantic	8/25/2009 through 8/26/2009

Education Investment Options

Course & Basic Follow-on Coaching	$1,600	REGISTER
Course & Comprehensive Follow-on Coaching	$2,200	REGISTER
Course Only	$1,400	REGISTER
Course Only	14 Training Credits	REGISTER
Basic Coaching ala Carte	Not currently offered	REGISTER
S3 Board & 1 hour support	$450	REGISTER
V4 Board & 1 hour support	$800	REGISTER
V5 Board & 1 hour support	$1,900	REGISTER

Basic follow-on coaching includes 2 hours (max 4 calls)

Comprehensive follow-on coaching includes 8 hours (max 12 calls)