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Advanced FPGA Implementation
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Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE™ 9.1i tool suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover Synplicity’s Synplify and the Xilinx XST tools. This course requires the Fundamentals of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months’ design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE software 9.1i tools and the Virtex™-4 FPGAs.
Level
Advanced
Duration
2 Days
Who Should Attend
Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity
Software Tools
Xilinx ISE 9.1i SP2
Synplicity Synplify Pro 8.8
Precision 2006.a
Skills Gained
After completing this training, you will have the necessary skills to:
Create and edit timing constraints in the UCF file
Utilize Tcl-based scripting to implement a design
Analyze I/O interface timing and implement timing constraints and design modifications to meet System and Source Synchronous I/O interface timing
Utilize Partitions and SmartGuide™ technology to preserve timing results
Demonstrate floorplanning techniques to enhance timing
Optimize the post-place-and-route design in the FPGA Editor for more efficient in-circuit testing
Course Outline
Introduction
Lab 1: Achieving Timing Closure
Section 1: Advanced Implementation Control
Tcl Scripting
Lab 2: Tcl Scripting
UCF Editing
Lab 3: UCF
Advanced I/O Timing
Lab 4: Advanced I/O Timing
Section 2: Design Preservation
SmartCompile Design Preservation Techniques
Lab 5: SmartCompile
Floorplanning Effective Layout
Lab 6: Floorplanning
Section 3: Reduce Debug Time
FPGA Editor: Viewing and Editing a Routed Design
Lab 7: FPGA Editor
Labs
Lab 1: Achieving Timing Closure – Create global timing constraints, read timing reports, apply path-specific constraints (multicycle and false paths), and apply advanced implementation options.
Lab 2: Tcl Scripting – Write program commands in a Tcl script file to implement the design. Then modify program switches to obtain the greatest possible performance from the design.
Lab 3: UCF – Write constraints directly into a UCF file to guide the performance results of implementation.
Lab 4: Advanced I/O Timing – Compose timing constraints for I/O interface. Analyze the timing failures and determine changes to correct the timing issues. Modify the design to fix timing failures.
Lab 5: SmartCompile – Utilize SmartGuide and Partitions to preserve timing results from one iteration to the next.
Lab 6: Floorplanning – Implement a design using floorlplanned constraints to enhance the timing results over a design without floorplanning.
Lab 7: FPGA Editor – Use the FPGA Editor to view and edit a design. Analyze the contents of a CLB; add a probe; remove, place, and modify components; and analyze long nets.
Prerequisites
- Fundamentals of FPGA Design course or equivalent knowledge
- Designing for Performance course or equivalent knowledge
- Intermediate HDL knowledge (VHDL or Verilog) is strongly recommended
- Solid digital design background
- At least six months' design experience with Xilinx tools and FPGAs is strongly recommended
No Scheduled Sessions
Contact Bottom Line Technologies for more information
Education Investment Options
| Course & Basic Follow-on Coaching |
$1,599 |
REGISTER |
| Course & Comprehensive Follow-on Coaching |
$2,199 |
REGISTER |
| Course Only |
$1,399 |
REGISTER |
| Basic Coaching ala Carte |
Not currently offered |
REGISTER |
| S3 Board & 1 hour support |
$399 |
REGISTER |
| V4 Board & 1 hour support |
$599 |
REGISTER |
| V5 Board & 1 hour support |
$1,399 |
REGISTER |
Basic follow-on coaching includes 2 hours (max 4 calls)
Comprehensive follow-on coaching includes 8 hours (max 12 calls)
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