HDL Coding Guidelines

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Table of Contents

Section	Topic	Page
1	Coding Guidelines / Design Rules	6
1.1	Style	6
1.1.1	Top-Down Design	6
1.1.1.1	Behavioral and Structural Code	6
1.1.1.2	Declarations, Instantiations, and Mappings	7
1.1.1.3	Inverted Signals	7
1.1.2	Comments	8
1.1.3	Indentation	9
1.1.4	Naming Conventions	10
1.1.4.1	Entities, Architectures, Procedures, and Functions	10
1.1.4.2	Signal Naming Conventions	11
1.2	Use of Signals and Variables	12
1.2.1	Signals	12
1.2.1.1	Casting	12
1.2.1.2	Signal Rules	13
1.2.1.3	Variable Use and Rules	13
1.3	Packages	14
1.3.1	Package Contents	15
1.3.1.1	Constants	15
1.3.1.2	Functions and Procedures	16
1.3.1.3	Types, Subtypes, and Aliases	17
1.4	Technology Specific Code (Xilinx � Virtex)	18
1.4.1	Instantiation	18
1.4.1.1	Required Instantiation	18
1.4.1.1.1	Simulation of Instantiated Xilinx Primitives	19
1.4.2	Non-Generic - Xilinx Specific Code	20
1.4.2.1	Tri-State MUX	20
1.4.2.2	Memory	21
1.4.2.2.1	RAM/ROM	21
1.4.2.2.2	COREGen	23
1.4.2.2.2.1	Xilinx BlockRAM FSM	23
1.4.2.3	Comparators	24
1.4.2.4	Xilinx Clock Enables	24
1.4.2.5	Pipelining with Virtex SRL	25
1.4.2.6	ASIC or FPGA? � Generate Statements	26
1.5	Coding for Synthesis	26
1.5.1	Logic Level Reduction	26
1.5.1.1	If-Then-Else and Case Statements	27
1.5.1.2	For Loops	28
1.5.2	Inadvertent Latch Inference	28
1.5.3	Synchronous Design	30
1.5.3.1	Pipelining	30
1.5.3.2	Registering Leaf-Level Outputs and Top-Level Inputs	30
1.5.3.3	Clock Enables	31
1.5.3.4	Local Synchronous Sets/Resets	32
1.5.3.5	Finite State Machines	32
1.5.3.5.1	Encoding Style	32
1.5.3.5.2	FSM VHDL Processes	33
1.5.3.5.3	Xilinx BlockRAM implementation of FSM	34