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Redges, Fedges, Tigers & Bears (Page 2 of 11)
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Potential Challenge: Clock distribution
The number of FPGA clock trees or networks has grown over the past decade, yet they remain a limited, hence, valuable resource. While the ASIC designer can implement any number of clock trees, even they do so at a cost.
Efficient and wise use of clock resources is also one of the easiest way to get software tools to work with, not against, you! Placement, routing, even timing tools work best when clock resources are used properly.
Unfortunately, as in the case of 64 channels, sometimes the number of clocks simply exceeds the available resources. We'll tackle that shortly.
Finally, the last place any designer wants to be is using general routing resources for clock distribution. Can today's tools do a better job with this? Yes. Is this an uphill, arduous, and often avoidable battle? Absolutely. "Discretion being the better part of valor" would have the wise designer avoid this situation entirely if possible.
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