Redges, Fedges, Tigers & Bears (Page 10 of 11)

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Issue: October 2005

Redges, Fedges, Tigers & Bears (Page 10 of 11)

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Redges & Fedges
Once subtle point: You may have noted the "Glitch" symbols at the output of the first Flip-flop and again at the output of the AND gate. This indicates that the metastability issues related to sampling still exist in the signal at this point. The metastability is resolved at the next register, where the Y-output is used as a Clock Enable to clock in the ChannelData.

FixMetastable _520x250.jpg

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